Landon Curt Noll
c0663537cb
The 2020 winners are hinted it, but the source code is not there,
nor are the hints. Someone could look into the HTML and
see what was commented out, but that is not a problem because
WHO won is known and the name of their AWARD is known already.
Moreover a number of the winners have talked about what their
entirs do, so the commented out spoiler text is not a bit problem.
One will find HTML commented out with:
<!-- XXX remove when 2020 is ready
2020 links here
XXX remove when 2020 is ready -->
The "XXX remove when 2020 is ready" string is found at the
start and end comment blocks. Again, soneone could read
what was commented out, but that is OK since most of that
information is known or can be known. The following files
have such HTML comment blocks in them.
./winners.html
./years-spoiler.html
./years.html
In addition, ./all/summary.txt was modified to not
include the 2020 entries for the momemt.
The 2020 winner code AND write-ups are NOT part of this set.
p.s. The all/all.tar.bz2 does not contain the 2020 source code (yet?).
324 lines
9.0 KiB
HCL
324 lines
9.0 KiB
HCL
# Four double-pole relay
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def r4 coil l3 nd3 nc3 l2 nd2 nc2 l1 nd1 nc1 l0 nd0 nc0 :
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r coil l3 nd3 nc3
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r coil l2 nd2 nc2
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r coil l1 nd1 nc1
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r coil l0 nd0 nc0
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# Buffer
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def buf input output :
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r input output 1 0
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# Inverter
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def inv input output :
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r input output 0 1
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# AND Gate
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def and i1 i0 o :
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r i0 z 1 0
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r i1 o z 0
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# NAND Gate
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def nand i0 i1 o :
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r i0 1 0 o
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r i1 1 0 o
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# OR Gate
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def or i0 i1 o :
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r i0 1 o 0
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r i1 1 o 0
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# NOR Gate
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def nor i0 i1 o :
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r i0 1 0 z
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r i1 z 0 o
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# XOR Gate
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def xor i0 i1 o :
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r i0 1 b a
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r i1 o a b
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# XNOR Gate
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def xnor i0 i1 o :
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r i0 1 a b
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r i1 o a b
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# Half Adder
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def halfAdder a b s1 s0 :
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and a b s1
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xor a b s0
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# Full Adder
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def fullAdder carryIn a b carryOut sum :
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halfAdder a b s1 s0
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halfAdder s0 carryIn carry sum
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or s1 carry carryOut
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# 2-bit Adder
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def adder2 carryIn a1 a0 b1 b0 carryOut s1 s0 :
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fullAdder carryIn a0 b0 carry s0
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fullAdder carry a1 b1 carryOut s1
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# 4-bit Adder
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def adder4 carryIn a3 a2 a1 a0 b3 b2 b1 b0 carryOut s3 s2 s1 s0 :
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adder2 carryIn a1 a0 b1 b0 carry s1 s0
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adder2 carry a3 a2 b3 b2 carryOut s3 s2
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# 8-bit Adder
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def adder8 carryIn
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a7 a6 a5 a4 a3 a2 a1 a0
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b7 b6 b5 b4 b3 b2 b1 b0
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carryOut s7 s6 s5 s4 s3 s2 s1 s0 :
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adder4 carryIn a3 a2 a1 a0 b3 b2 b1 b0 carry s3 s2 s1 s0
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adder4 carry a7 a6 a5 a4 b7 b6 b5 b4 carryOut s7 s6 s5 s4
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# Konrad Zuse Dual-Rail-Carry Full Adder
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def zuseFullAdder carryInNeg carryIn a b carryOutNeg carryOut sum :
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r4 a carryInNeg y z sum w x 1 v y carryIn u v
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r4 b carryOutNeg z y carryInNeg x w carryIn w x carryOut v u
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# Konrad Zuse Dual-Rail-Carry 2-bit Adder
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def zuseAdder2 carryInNeg carryIn a1 a0 b1 b0 carryOutNeg carryOut s1 s0 :
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zuseFullAdder carryInNeg carryIn a0 b0 cOutNeg cOut s0
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zuseFullAdder cOutNeg cOut a1 b1 carryOutNeg carryOut s1
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# Konrad Zuse Dual-Rail-Carry 4-bit Adder
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def zuseAdder4 carryInNeg carryIn a3 a2 a1 a0 b3 b2 b1 b0
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carryOutNeg carryOut s3 s2 s1 s0 :
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zuseAdder2 carryInNeg carryIn a1 a0 b1 b0 cOutNeg cOut s1 s0
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zuseAdder2 cOutNeg cOut a3 a2 b3 b2 carryOutNeg carryOut s3 s2
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# Konrad Zuse Dual-Rail-Carry 8-bit Adder
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def zuseAdder8 carryInNeg carryIn
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a7 a6 a5 a4 a3 a2 a1 a0
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b7 b6 b5 b4 b3 b2 b1 b0
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carryOutNeg carryOut s7 s6 s5 s4 s3 s2 s1 s0 :
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zuseAdder4 carryInNeg carryIn a3 a2 a1 a0 b3 b2 b1 b0 cOutNeg cOut s3 s2 s1 s0
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zuseAdder4 cOutNeg cOut a7 a6 a5 a4 b7 b6 b5 b4
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carryOutNeg carryOut s7 s6 s5 s4
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# 1-bit Partial Adder/Subtractor
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def xFullAdder subtract carryInNeg carryIn a b carryOutNeg carryOut sum :
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xor subtract b bNeg
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zuseFullAdder carryInNeg carryIn a bNeg carryOutNeg carryOut sum
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# 2-bit Partial Adder/Subtractor
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def xFullAdder2 subtract carryInNeg carryIn
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a1 a0 b1 b0 carryOutNeg carryOut s1 s0 :
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xFullAdder subtract carryInNeg carryIn a0 b0 cOutNeg cOut s0
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xFullAdder subtract cOutNeg cOut a1 b1 carryOutNeg carryOut s1
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# 4-bit Partial Adder/Subtractor
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def xFullAdder4 subtract carryInNeg carryIn a3 a2 a1 a0 b3 b2 b1 b0
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carryOutNeg carryOut s3 s2 s1 s0 :
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xFullAdder2 subtract carryInNeg carryIn a1 a0 b1 b0 cOutNeg cOut s1 s0
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xFullAdder2 subtract cOutNeg cOut a3 a2 b3 b2 carryOutNeg carryOut s3 s2
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# 8-bit Partial Adder/Subtractor
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def xFullAdder8 subtract carryInNeg carryIn
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a7 a6 a5 a4 a3 a2 a1 a0
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b7 b6 b5 b4 b3 b2 b1 b0
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carryOutNeg carryOut s7 s6 s5 s4 s3 s2 s1 s0 :
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xFullAdder4 subtract carryInNeg carryIn a3 a2 a1 a0 b3 b2 b1 b0
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cOutNeg cOut s3 s2 s1 s0
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xFullAdder4 subtract cOutNeg cOut a7 a6 a5 a4 b7 b6 b5 b4
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carryOutNeg carryOut s7 s6 s5 s4
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# 8-bit Adder/Subtractor
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def adderSubtractor subtract
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a7 a6 a5 a4 a3 a2 a1 a0
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b7 b6 b5 b4 b3 b2 b1 b0
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carryOut s7 s6 s5 s4 s3 s2 s1 s0 :
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inv subtract carryInNeg
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xFullAdder8 subtract carryInNeg subtract
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a7 a6 a5 a4 a3 a2 a1 a0
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b7 b6 b5 b4 b3 b2 b1 b0
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carryOutNeg cOut s7 s6 s5 s4 s3 s2 s1 s0
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xor cOut subtract carryOut
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# 2-to-1 Mux
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def mux a i1 i0 o :
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r a o i1 i0
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# 4-to-1 Mux
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def mux4to1 a1 a0 i3 i2 i1 i0 o :
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mux a0 i1 i0 x
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mux a0 i3 i2 y
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mux a1 y x o
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# 8-to-1 Mux
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def mux8to1 a2 a1 a0 i7 i6 i5 i4 i3 i2 i1 i0 o :
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mux4to1 a1 a0 i3 i2 i1 i0 x
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mux4to1 a1 a0 i7 i6 i5 i4 y
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mux a2 y x o
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# 3-to-8 Decoder
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def decoder3to8 a2 a1 a0 o7 o6 o5 o4 o3 o2 o1 o0 :
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mux8to1 a2 a1 a0 o7 o6 o5 o4 o3 o2 o1 o0 1
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def trans enabled a b :
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r enabled a b 0
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# 2-bit transmission gate
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def trans2 enabled a1 a0 b1 b0 :
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trans enabled a1 b1
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trans enabled a0 b0
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# 4-bit transmission gate
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def trans4 enabled a3 a2 a1 a0 b3 b2 b1 b0 :
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trans2 enabled a3 a2 b3 b2
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trans2 enabled a1 a0 b1 b0
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# 8-bit transmission gate
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def trans8 enabled a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 :
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trans4 enabled a7 a6 a5 a4 b7 b6 b5 b4
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trans4 enabled a3 a2 a1 a0 b3 b2 b1 b0
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# 16-bit transmission gate
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def trans16 enabled
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a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
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b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 :
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trans8 enabled a15 a14 a13 a12 a11 a10 a9 a8 b15 b14 b13 b12 b11 b10 b9 b8
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trans8 enabled a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0
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# Latch, stores when w = 1
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def latch w d q :
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mux w d q z
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buf z q
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# Latch, stores when w = 0
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def latchNeg w d q :
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mux w q d z
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buf z q
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# Flip flop, stores when w rises to 1, expresses new value when w drops to 0
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def flipFlop w d q :
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latch w d q2
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latchNeg w q2 q
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def flipFlopRegister w d7 d6 d5 d4 d3 d2 d1 d0 q7 q6 q5 q4 q3 q2 q1 q0:
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flipFlop w d7 q7
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flipFlop w d6 q6
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flipFlop w d5 q5
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flipFlop w d4 q4
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flipFlop w d3 q3
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flipFlop w d2 q2
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flipFlop w d1 q1
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flipFlop w d0 q0
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def latchRegister w d7 d6 d5 d4 d3 d2 d1 d0 q7 q6 q5 q4 q3 q2 q1 q0:
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latch w d7 q7
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latch w d6 q6
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latch w d5 q5
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latch w d4 q4
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latch w d3 q3
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latch w d2 q2
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latch w d1 q1
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latch w d0 q0
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def tinyLatchRegister writeNeg d7 d6 d5 d4 d3 d2 d1 d0 :
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r d7 d7 writeNeg 0
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r d6 d6 writeNeg 0
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r d5 d5 writeNeg 0
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r d4 d4 writeNeg 0
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r d3 d3 writeNeg 0
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r d2 d2 writeNeg 0
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r d1 d1 writeNeg 0
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r d0 d0 writeNeg 0
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def memoryRegister select load d7 d6 d5 d4 d3 d2 d1 d0 :
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inv load writeNeg
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inv writeNeg select
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trans8 select d7 d6 d5 d4 d3 d2 d1 d0 z7 z6 z5 z4 z3 z2 z1 z0
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tinyLatchRegister writeNeg z7 z6 z5 z4 z3 z2 z1 z0
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# 2 Bytes of memory
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def memory2 address select load d7 d6 d5 d4 d3 d2 d1 d0 :
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mux address select1 select0 select
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mux address load1 load0 load
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memoryRegister select0 load0 d7 d6 d5 d4 d3 d2 d1 d0
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memoryRegister select1 load1 d7 d6 d5 d4 d3 d2 d1 d0
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# 4 Bytes of memory
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def memory4 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0 :
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mux a1 select1 select0 select
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mux a1 load1 load0 load
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memory2 a0 select load d7 d6 d5 d4 d3 d2 d1 d0
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memory2 a0 select load d7 d6 d5 d4 d3 d2 d1 d0
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# 8 Bytes of memory
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def memory8 a2 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0 :
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mux a2 select1 select0 select
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mux a2 load1 load0 load
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memory4 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0
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memory4 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0
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# 16 Bytes of memory
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def memory16 a3 a2 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0 :
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mux a3 select1 select0 select
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mux a3 load1 load0 load
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memory8 a2 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0
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memory8 a2 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0
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# 32 Bytes of memory
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def memory32 a4 a3 a2 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0 :
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mux a4 select1 select0 select
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mux a4 load1 load0 load
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memory16 a3 a2 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0
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memory16 a3 a2 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0
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# 64 Bytes of memory
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def memory64 a5 a4 a3 a2 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0 :
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mux a5 select1 select0 select
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mux a5 load1 load0 load
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memory32 a4 a3 a2 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0
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memory32 a4 a3 a2 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0
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# 128 Bytes of memory
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def memory128 a6 a5 a4 a3 a2 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0 :
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mux a6 select1 select0 select
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mux a6 load1 load0 load
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memory64 a5 a4 a3 a2 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0
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memory64 a5 a4 a3 a2 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0
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# 256 Bytes of memory
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def memory256 a7 a6 a5 a4 a3 a2 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0 :
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mux a7 select1 select0 select
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mux a7 load1 load0 load
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memory128 a6 a5 a4 a3 a2 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0
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memory128 a6 a5 a4 a3 a2 a1 a0 select load d7 d6 d5 d4 d3 d2 d1 d0
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def counterElement andIn andOut value :
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xor andIn value data
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flipFlop c data value
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and andIn value andOut
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def counter2 andIn andOut v1 v0 :
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counterElement andIn x v0
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counterElement x andOut v1
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def counter4 andIn andOut v3 v2 v1 v0 :
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counter2 andIn x v1 v0
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counter2 x andOut v3 v2
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def counter8 andIn andOut v7 v6 v5 v4 v3 v2 v1 v0 :
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counter4 andIn x v3 v2 v1 v0
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counter4 x andOut v7 v6 v5 v4
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def shift2 shiftIn q1 q0 :
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flipFlop c shiftIn q1
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flipFlop c q1 q0
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def shift4 shiftIn q3 q2 q1 q0 :
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shift2 shiftIn q3 q2
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shift2 q2 q1 q0
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def shift8 shiftIn q7 q6 q5 q4 q3 q2 q1 q0 :
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shift4 shiftIn q7 q6 q5 q4
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shift4 q4 q3 q2 q1 q0
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run 100 5 shift8 1 ? ? ? ? ? ? ? ?
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